Establishment profile
GENESIC SEMICONDUCTOR INC
43670 TRADE CENTER PLACE, DULLES, VA, 20166
334413 — Semiconductor and Related Device Manufacturing
Summary
GENESIC SEMICONDUCTOR INC has accumulated 3 OSHA violations across 1 inspection over 15 years of recorded history, with $73 in total assessed penalties.
The establishment sits in the 60th percentile for violations within its industry-state peer group of 44 employers. The most recent enforcement activity was recorded 15 years ago.
Federal records were found in 1 of 15 sources. Sources without matching records returned empty for this establishment.
Agency coverage
GENESIC SEMICONDUCTOR INC appears in OSHA workplace safety record only. No matching records were found in WHD wage enforcement, MSHA mine safety, EPA environmental compliance, NLRB labor relations, OFLC visa and labor certification (historical), FMCSA motor carrier registration, SAM.gov federal debarment, CMS nursing home enforcement, UVA Corporate Prosecution Registry, CPSC product recalls, or NHTSA vehicle recalls. Single-agency enforcement records typically indicate either a discrete incident-based inspection or a low-risk operational profile.
OSHA workplace safety
100% of inspections at this establishment produced violations,
Most-cited OSHA standards
Top OSHA standards cited at this employer, ranked by citation count. Standards (CFR sections) cluster citations into safety themes -- machine guarding, lockout-tagout, hazard communication, fall protection, process safety, etc. A concentration on one or two sections reveals a pattern that individual citations don’t. 3 distinct standards shown · 3 citations in this view · $73 in penalties.
| CFR section | Citations | Inspections | Total penalty | First cited | Last cited |
|---|---|---|---|---|---|
| 29 CFR 1910.0037 A03 | 1 | 1 | $73 | Jul 2011 | Jul 2011 |
| 29 CFR 1910.0334 A02 I | 1 | 1 | — | Jul 2011 | Jul 2011 |
| 29 CFR 1910.1200 G08 | 1 | 1 | — | Jul 2011 | Jul 2011 |
Source: OSHA inspection citations (violation_detail). CFR section codes can be looked up at osha.gov/laws-regs for the formal standard text. Per-inspection detail and the specific violation descriptions are available by expanding individual inspections below.
Peer comparison
Above average violations in NAICS 3344 within VA. Peer group: 44 employers. This establishment has 3 OSHA violations; peer median is 2.
Safety self-report (OSHA 300A)
No self-reported injury rates filed with OSHA's Injury Tracking Application for GENESIC SEMICONDUCTOR INC. Verify directly with OSHA Injury Tracking Application →
Industry benchmark
BLS rates reflect industry-wide averages. Self-reported figures come from OSHA’s Injury Tracking Application; absence of self-reported data does not necessarily indicate non-compliance — many establishments fall below the ITA reporting threshold.
Inspection breakdown
Complaint- and accident-triggered inspections are stronger risk signals than routine planned inspections.
OSHA severe injury reports
No severe injury reports (hospitalization, amputation, or loss of an eye) on file under 29 CFR 1904.39 for GENESIC SEMICONDUCTOR INC. Verify directly with Occupational Safety and Health Administration →
Activity timeline
No federal enforcement activity has been recorded against this establishment in 15+ years. Most recent activity: 15 years ago. Data on this page is refreshed weekly.
Wage & Hour Division (WHD)
No WHD wage, overtime, or child-labor enforcement cases on file for GENESIC SEMICONDUCTOR INC. Verify directly with Wage and Hour Division →
Mine safety (MSHA)
No MSHA mine safety violations on file for GENESIC SEMICONDUCTOR INC. Verify directly with Mine Safety and Health Administration →
Labor relations (NLRB)
No NLRB unfair labor practice charges or union representation cases on file for GENESIC SEMICONDUCTOR INC. Verify directly with National Labor Relations Board →
Visa & labor certification (OFLC) — historical
No H-1B, H-2A, or H-2B labor condition applications on file (historical data only — DOL ended OFLC publication) for GENESIC SEMICONDUCTOR INC. Verify directly with Office of Foreign Labor Certification →
Environmental compliance (EPA)
No EPA inspections or formal enforcement actions on file for GENESIC SEMICONDUCTOR INC. Verify directly with Environmental Protection Agency →
Federal criminal prosecution record
No federal criminal prosecutions, plea agreements, or deferred-prosecution agreements on file for GENESIC SEMICONDUCTOR INC. Verify directly with UVA Corporate Prosecution Registry →
Federal contracts
This location
- Department of DefensePERFORMANCE, YEILD, AND COST IMPROVEMENT FOR HIGH VOLUMEcontract · Last action 2025-05-07$4,650,000
- Department of DefensePERFORMANCE, YIELD, AND COST IMPROVEMENT TO MEDIUM VOLTAGE SIC MOSFETScontract · Last action 2024-09-03$3,384,638
- Department of DefenseIGF::OT::IGF RESEARCH AND DEVELOPMENTcontract · Last action 2025-05-07$1,999,935
- Department of DefenseSBIR PHASE ** FOR TOPIC: A16-066contract · Last action 2025-05-07$1,829,110
- National Aeronautics and Space AdministrationIGF::OT::IGF CAPITALIZING ON A STRONG EXPERTISE IN III-NITRIDE EPITAXY, GAN-SI POWER DEVICE DESIGNS, AND WIDEBANDGAP POWER ELECTRONICS, RESEARCHERS AT GENESIC SEMICONDUCTOR PROPOSE A SBIR PROGRAM FOCUSED ON THE DEVELOPMENT OF 15 KW/300C-RATED POWER CONVERTERS USING ALGAN/GAN-SI MOS-HFETS AND SCHOTTKY RECTIFIERS. THE PROPOSED ALGAN/GAN-SI POWER CONVERTERS TO BE DEVELOPED IN THIS PROGRAM WILL USHER IN A NEW GENERATION OF HIGH-EFFICIENCY, LOW-COST, AND RADIATION-HARD POWER CONVERSION UNITS ON-BOARD FUTURE NASA SPACECRAFT. PHASE I OF THIS PROPOSED WORK FOCUSSED ON THE OPTIMIZATION OF THE DESIGN AND FABRICATION OF THE ALGAN/GAN-SI MOS-HFET AND NSJ SBR DEVICES. PHASE II WILL BE FOCUSED ON THE DESIGN AND INTEGRATION OF SI/GAN GATE-DRIVE CIRCUITRY WITH THE POWER SBRS AND TRANSISTORS TO CREATE HIGH-POWER INTEGRATED CIRCUITS. ANOTHER MAJOR OBJECTIVE DURING PHASE II WILL BE THE CONSTRUCTION OF RAD-HARD PACKAGING FOR THE POWER ICS. AT THE END OF PHASE II OF THIS PROGRAM, A FULLYFUNCTIONAL 15 KW/300C RATED POWER CONVERTER IC EQUIPPED WITH ALGAN/GAN-ON-SI MOS-HFETS, NATURAL SUPERJUNCTION (NSJ) SBRS AS FREE-WHEELING DIODES AND ON-CHIP SIC OR III-NITRIDE GATE DRIVE CIRCUITRY WILL BE DEMONSTRATED AT A SWITCHING FREQUENCY OF 1 MHZ AND AT A TEMPERATURE OF 300C. AS COMPARED TO THE EXISTING STATE-OF-THE-ART POWER ELECTRONICS TECHNOLOGY, THE PROPOSED ALGAN/GAN-ON-SI POWER CONVERTERS WILL OFFER (A) LOWER ON-STATE LOSSES, 300C OPERATION AND 1 MHZ SWITCHING CAPABILITY (B) A LATERAL DEVICE ARCHITECTURE, WHICH IS HIGHLY DESIRABLE FOR CONSTRUCTION FOR MONOLITHIC POWER INTEGRATED CIRCUITS (C) POSSIBILITY OF HYBRID INTERCONNECTION OF III-NITRIDE POWER DEVICES WITH ON-CHIP RAD-HARD ALGAN/GAN GATE DRIVE CIRCUITRY (D) DESIRABLE NORMALLY-OFF POWER SWITCHEScontract · Last action 2016-04-13$1,499,992
- Department of DefenseRESEARCH AND DEVELOPMENTcontract · Last action 2025-05-07$1,450,347
- Department of DefensePHASE II SBIRcontract · Last action 2025-05-07$1,396,860
- National Aeronautics and Space AdministrationIGF::OT::IGF THIS TWO-PHASE SBIR PROGRAM TARGETS THE NEED FOR HIGHLY INTEGRATED SIC-BASED ELECTRONICS SYSTEMS BY DEVELOPING GATE DRIVE CIRCUITRY THAT CAN BE FULLY INTEGRATED WITH 4H-SIC POWER SWITCHING DEVICES, ENABLING EVENTUAL REALIZATION OF A MONOLITHIC POWER SWITCHING PLATFORM. SPECIFICALLY, THE FINAL GOAL OF THIS PROGRAM IS TO DEVELOP AND DEMONSTRATE A FULLY INTEGRATED, ISOLATED GATE DRIVER ARCHITECTURE, HAVING AN INTEGRATED SIC POWER MOSFET. IN ADDITION TO INTEGRATED RESISTORS AND CAPACITORS, DEVELOPMENT OF SIC CMOS TECHNOLOGY WILL ENTAIL THE DEMONSTRATION OF LATERAL SIC NMOSFETS AND THE MORE CHALLENGING SIC PMOSFET DEVICES WITH ADEQUATE PERFORMANCE AND RADIATION HARDNESS. DURING PHASE I, AN NMOS-ONLY GATE DRIVE BUFFER CIRCUIT WAS DESIGNED AND IMPLEMENTED ON THE SAME HOST SUBSTRATE USED FOR FABRICATING 1200 V SIC DMOSFETS. PHASE II WILL FOCUS ON INTEGRATING THE GATE DRIVE BUFFER IC FABRICATED DURING PHASE I WITH A 1200 V RATED POWER SIC DMOSFET. PROCESS AND DEVICE DEVELOPMENT OF A SIC PMOS TECHNOLOGY WILL BE CONDUCTED DURING PHASE II, IN PURSUIT OF A SIC CMOS GATE DRIVE CIRCUIT. THE FABRICATED POWER AND LATERAL SIC DEVICES WILL BE SUBJECTED TO EXTENSIVE RADIATION TESTING TO INVESTIGATE THE DEGRADATION PATHWAYS OF THIS MONOLITHIC POWER SWITCHING DEVICE, WHEN EXPOSED TO HIGH RADIATION ENVIRONMENTS.contract · Last action 2019-04-29$755,000
- Department of DefenseSBIRcontract · Last action 2016-01-19$749,991
- Department of DefenseRESEARCH AND DEVELOPMENT IN THE PHYSICAL, ENGINEERING, AND LIFE SCIENCES (EXCEPT BIOTECHNOLOGY)contract · Last action 2025-05-07$749,979
- Department of DefensePROGRESS REPORTcontract · Last action 2019-06-21$229,998
- National Aeronautics and Space AdministrationIGF::OT::IGF CAPITALIZING ON A POTENT CONFLUENCE OF EXPERTISE IN III-NITRIDE EPITAXY, GAN-SI POWER DEVICE DESIGNS, AND WIDE-BANDGAP POWER ELECTRONICS, RESEARCHERS AT GENESIC SEMICONDUCTOR AND CORNELL UNIVERSITY JOINTLY PROPOSE A SBIR PROGRAM FOCUSED ON THE DEVELOPMENT OF 15 KW/300 C-RATED POWER CONVERTERS USING ALGAN/GAN-SI MOS-HFETS AND SCHOTTKY RECTIFIERS. THE PROPOSED ALGAN/GAN-SI POWER CONVERTERS TO BE DEVELOPED IN THIS PROGRAM WILL USHER IN A NEW GENERATION OF HIGH-EFFICIENCY, LOW-COST, AND RADIATION-HARD POWER CONVERSION UNITS ON-BOARD FUTURE NASA SPACECRAFT. PHASE I OF THIS PROPOSED WORK WILL FOCUS ON THE OPTIMIZATION OF THE DESIGN AND FABRICATION OF THE ALGAN/GAN-SI MOS-HFET AND NSJ SBR DEVICES. PHASE II WILL BE FOCUSED ON THE DESIGN AND INTEGRATION OF SI/GAN GATE-DRIVE CIRCUITRY WITH THE POWER SBRS AND TRANSISTORS TO CREATE HIGH-POWER INTEGRATED CIRCUITS. ANOTHER MAJOR OBJECTIVE DURING PHASE II WILL BE THE CONSTRUCTION OF RAD-HARD PACKAGING FOR THE POWER ICS. AT THE END OF PHASE II OF THIS PROGRAM, A FULLY-FUNCTIONAL 15 KW/300 C RATED POWER CONVERTER IC EQUIPPED WITH ALGAN/GAN-ON-SI MOS-HFETS, NATURAL SUPERJUNCTION (NSJ) SBRS AS FREE-WHEELING DIODES AND ON-CHIP SIC OR III-NITRIDE GATE DRIVE CIRCUITRY WILL BE DEMONSTRATED AT A SWITCHING FREQUENCY OF 1 MHZ AND AT A TEMPERATURE OF 300 C. AS COMPARED TO THE EXISTING STATE-OF-THE-ART POWER ELECTRONICS TECHNOLOGY, THE PROPOSED ALGAN/GAN-ON-SI POWER CONVERTERS WILL OFFER (A) LOWER ON-STATE LOSSES, 300 C OPERATION AND 1 MHZ SWITCHING CAPABILITY (B) A LATERAL DEVICE ARCHITECTURE, WHICH IS HIGHLY DESIRABLE FOR CONSTRUCTION FOR MONOLITHIC POWER INTEGRATED CIRCUITS (C) POSSIBILITY OF HYBRID INTERCONNECTION OF III-NITRIDE POWER DEVICES WITH ON-CHIP RAD-HARD ALGAN/GAN GATE DRIVE CIRCUITRY (D) DESIRABLE NORMALLY-OFF POWER SWITCHES.contract · Last action 2013-08-16$199,766
- Department of DefenseSBIR PHASE I RESEARCH STUDYcontract · Last action 2021-07-29$167,497
- Department of DefenseIGF::OT::IGF SOLID STATE HIGH VOLTAGE SWITCHING DEVICE FOR MULTI-POINT INITIATION SBIR PHASE I.contract · Last action 2017-07-31$150,000
- Department of DefenseIGF::CT::IGF ROBUST SIC MOSFET BASED POWER MODULES (N161-066-0489)contract · Last action 2017-04-12$150,000
- National Aeronautics and Space AdministrationIGF::OT::IGF THIS TWO-PHASE SBIR PROGRAM TARGETS THE NEED FOR HIGHLY INTEGRATED SIC-BASED ELECTRONICS SYSTEMS BY DEVELOPING ANALOG AND DIGITAL CIRCUITS THAT CAN BE FULLY INTEGRATED WITH 4H-SIC POWER SWITCHING DEVICES, ENABLING EVENTUAL REALIZATION OF A MONOLITHIC, HIGHLY INTEGRATED GATE DRIVER CIRCUIT. SPECIFICALLY, THE FINAL GOAL OF THIS PROGRAM IS TO DEVELOP AND DEMONSTRATE A FULLY INTEGRATED, ISOLATED, HIGH-SIDE/LOW-SIDE GATE DRIVER ARCHITECTURE, HAVING AN INTEGRATED SIC POWER MOSFET. IN ADDITION TO INTEGRATED RESISTORS AND CAPACITORS, DEVELOPMENT OF SIC CMOS TECHNOLOGY WILL ENTAIL THE DEMONSTRATION OF LATERAL SIC NMOSFETS AND THE MORE CHALLENGING SIC PMOSFET DEVICES WITH ADEQUATE PERFORMANCE AND RADIATION HARDNESS. DURING PHASE I, THE DEVELOPMENT OF A RAD-HARD SIC PMOS PROCESS WILL BE INVESTIGATED. IN PARALLEL, CAPITALIZING ON GENESIC?S ALREADY DEVELOPED SIC NMOS PROCESS, AN NMOS-ONLY GATE DRIVE BUFFER CIRCUIT WILL BE DESIGNED AND IMPLEMENTED ON THE SAME HOST SUBSTRATE AS 1200 V SIC DMOSFETS. COMPACT DEVICE MODELS WILL BE GENERATED DURING PHASE II FROM THE RESULTS OF THE SIC NMOS/PMOS PROCESS DEVELOPMENT. PENDING SUCCESSFUL DEVELOPMENT OF A RAD-HARD SIC PMOS PROCESS DURING PHASE I, PHASE II WILL FOCUS ON BUILDING AN ENTIRE SIC CMOS-BASED GATE DRIVE CIRCUIT AND INTEGRATING IT WITH A 1200 V SIC DMOSFET.contract · Last action 2017-01-13$125,000
- National Aeronautics and Space AdministrationIGF::OT::IGF THE PROPOSED SBIR PROGRAM TARGETS THE DEVELOPMENT OF RAD-HARD BY DESIGN (RHBD), 1200 V-CLASS SIC (PLANAR) VERTICAL DMOSFETS AND POWER SCHOTTKY RECTIFIERS FOR FUTURE NASA SPACE MISSIONS. SINGLE DIE RATINGS OF>1200 V,>75 A,>225?C AND COMPLIANCE TO A NASA-CERTIFIED RADIATION HARDNESS ASSURANCE PROGRAM ARE TARGETED FOR THE PROPOSED SIC POWER DEVICES. THE TARGET APPLICATION FOR THESE DEVICES INVOLVES A 30 KW POWER PROCESSOR UNIT (PPU) ON-BOARD A HALL THRUSTER PROPULSION SYSTEM OPERATING AT A 300-400 V (AVERAGE) DC BIAS WITH A PEAK VOLTAGE OF 600 V. SEVERAL INNOVATIVE DEVICE DESIGNS AND PROCESS STEPS FOR FABRICATING RHBD SIC POWER DMOSFETS AND SCHOTTKY RECTIFIERS WILL BE DEVELOPED DURING PHASE I. BUILDING ON THE DEVICE DEVELOPMENT CONDUCTED DURING PHASE I, THE DESIGN AND FABRICATION OF TRAVELED GUIDED 1200 V/75 A SIC DMOSFET AND SCHOTTKY RECTIFIER WAFER LOTS WILL BE CONDUCTED DURING THE PHASE II PROGRAM. THE EXISTING PACKAGING TECHNIQUES WILL BE MODIFIED FOR MEETING THE REQUIRED RADIATION STANDARDS FROM NASA. SELECTED DIE FROM BOTH PHASES OF THE PROPOSED PROGRAM WILL BE PACKAGED IN APPROPRIATE HEADERS FOR CONTROLLED DOSE RADIATION TESTING AS PER NASA REQUIREMENTS. A RIGOROUS SPACE-LEVEL (JANS) QUALIFICATION WILL BE CONDUCTED ON THE FABRICATED DEVICES DURING PHASE II. PHASE II WILL CULMINATE WITH THE INSERTION OF THE SIC POWER DMOSFETS AND SCHOTTKY RECTIFIERS INTO A 30 KW POWER PROCESSING UNIT (PPU) RELEVANT TO A NASA ELECTRIC PROPULSION SYSTEM AND DEMONSTRATING STABLE OPERATION.contract · Last action 2015-05-22$125,000
- Department of DefenseSBIR PHASE Icontract · Last action 2009-07-24$119,938
- National Aeronautics and Space AdministrationMONOLITHIC INTEGRATED SIC SUPER JUNCTION TRANSISTOR-JBS DIODE (MIDSJT) DEVICES ARE USED TO CONSTRUCT 500 OC CAPABLE MOTOR CONTROL POWER MODULES FOR DIRECT INTEGRATION WITH THE EXPLORATION ROVERS REQUIRED TO OPERATE IN VENUS-LIKE ENVIRONMENTS. THE PHASE I OF THIS PROPOSED WORK WILL FOCUS ON THE INTEGRATED MIDSJT DEVICE DEVELOPMENT AND HIGH-TEMPERATURE PACKAGING. PHASE II WILL FOCUS ON THE INTEGRATION OF THE MIDSJT DEVICES TO CONSTRUCT FULL 3-PHASE INVERTER MOTOR CONTROL MODULES. ALTHOUGH SIC IS THE SEMICONDUCTOR MATERIAL OF CHOICE FOR FABRICATING HIGH-TEMPERATURE (>150 OC) POWER ELECTRONICS, EXISTING SIC MOSFET AND JFET BASED TRANSISTOR DEVICE TECHNOLOGIES PERFORM POORLY AT TEMPERATURES EXCEEDING 200 OC. THE PROPOSED GATE OXIDE-FREE INTEGRATED MIDSJT DEVICE TECHNOLOGY WILL OVERCOME SEVERAL PROBLEMS ASSOCIATED WITH EXISTING SIC DEVICE TECHNOLOGIES BY: (A) EXHIBITING DESIRABLE NORMALLY-OFF OPERATION YET BEST-IN-CLASS ON-STATE CHARACTERISTICS AT TEMPERATURES AS HIGH AS 500 OC, (B) ELIMINATING PARASITIC INDUCTANCES/CAPACITANCES ASSOCIATED WITH INTERCONNECTING DISCRETE DEVICES, AND (C) ELIMINATING HIGH-TEMPERATURE GATE OXIDE RELIABILITY ISSUES. SPECIAL DEVICE DESIGNS AND FABRICATION PROCESSES WILL BE INVESTIGATED IN THIS WORK FOR RELIABLE DEVICE OPERATION AT 500 OC. NOVEL POWER DEVICE PACKAGING TECHNIQUES IN THE AREAS OF POWER SUBSTRATE, DIE-ATTACH, CHIP METALLIZATION AND WIRE BONDS WILL BE EXPLORED TO DEMONSTRATE RELIABLE MODULE OPERATION AT 500 OC AFTER SEVERAL THERMAL CYCLES.contract · Last action 2011-07-27$100,000
- Department of CommerceSBIR PHASE I AWARDcontract · Last action 2008-11-04$90,000
- Department of DefenseSBIR RESEARCHcontract · Last action 2008-07-25$69,911
- National Aeronautics and Space AdministrationHIGH TEMPERATURE APPLICATIONS - SIC RECTIFIERS, SIC PIN RECTIFIERS, SIC JUNCTION TRANSISTORScontract · Last action 2014-07-29$11,069
- Department of CommerceSAPPHIRE WAFERScontract · Last action 2016-01-26$920
Federal contract dollars to this establishment. Primary NAICS: 541715 - RESEARCH AND DEVELOPMENT IN THE PHYSICAL, ENGINEERING, AND LIFE SCIENCES (EXCEPT NANOTECHNOLOGY AND BIOTECHNOLOGY). Last action: 2025-05-07. Source: USAspending.gov, net obligations. Recipient address is the SAM registration / HQ address, not necessarily the worksite.
Inspection history
| Date | Trigger | Violations | Serious | Penalty | |
|---|---|---|---|---|---|
| 2011-06-21 | Planned | 3 | 1 | $73 |
Source: OSHA IMIS. Citation amounts reflect initially assessed penalties; final amounts after appeal may differ.
In the news
Other employers in this industry and state
Other employers in semiconductor and related device manufacturing within VA, ordered by federal enforcement volume:
- FORCE INC.CHRISTIANSBURG — 1 federal enforcement record
- MICROXACT, INC.RADFORD — 1 federal enforcement record
- MICRON TECHNOLOGY, INC.MANASSAS — 0 federal enforcement records
Related searches
- Semiconductor and Related Device ManufacturingAll employers in this industry
- Employers in VAState-wide enforcement data
- Semiconductor and Related in VAIndustry × state cross-filter
About this data
This profile aggregates federal enforcement records on GENESIC SEMICONDUCTOR INC from every major federal compliance and enforcement source plus the UVA Corporate Prosecution Registry. OSHA workplace safety inspections, WHD wage cases, MSHA mine safety, EPA environmental enforcement, NLRB labor relations, OFLC visa/labor certification, FMCSA motor carrier registration, SAM.gov debarments, CMS nursing-home records, BLS industry safety benchmarks, OSHA ITA self-reported injury rates, SEC enforcement and financial disclosures, CPSC and NHTSA recalls.
Establishments are matched across agencies using normalized employer name, state, and ZIP code.
OSHA citations typically appear 3–8 months after the inspection, so very recent enforcement actions may not yet be reflected. Profiles may be incomplete if the establishment operates under multiple legal names or files under variations our entity-matching rules don’t yet cover. To report a missing record or correction, email corrections@fastdol.com.
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Contact sales →Frequently asked
- What is GENESIC SEMICONDUCTOR INC's OSHA violation history?
- GENESIC SEMICONDUCTOR INC has 1 OSHA inspection on record with 3 violations and $73 in total penalties.
- How does GENESIC SEMICONDUCTOR INC's safety record compare to its industry?
- GENESIC SEMICONDUCTOR INC operates in the semiconductor and related device manufacturing industry. The industry average Total Recordable Incident Rate (TRIR) is 0.8.